The VHDL package does not compile

I am new to VHDL and I'm using VIvado 2017.1. I'm trying to use a package to define constants and other such enumerated types to include in multiple models. Right now however, I am unable to use the package in my model. I keep getting Error: Cannot f

Xilinx device-specific primitives

I need a list of device-specific primitives of Xilinx devices. I know that ISE has a list of templates and there are also PDF user guides but I need them as list of files in a folder so that I can parse them and extract name and port-list of every mo

Zynq bare metal assembly program without Vivado / SDK

I have a question for those familiar with the Xilinx Zynq and associated design tools.... Is it possible to compile and run C code for the Zynq 7010 (Zybo dev board), WITHOUT using the Xilinx toolchain (Vivado/SDK)? Is it possible to assemble and run

Use a type before it is declared in VHDL (2008)

Is it possible in any version of VHDL, maybe in 2008, to use a type before it's declared? E.g. I have this array declaration in the architecture of an entity: type my_array is array (integer range <>) of my_type; And still in the same architecture s

Forced VHDL input to ground

I am new to VHDL. I was trying to write code for adder subtractor. One of my input bus for the circuity is connected to ground after synthesis. I am using Xilinx ISE 14.2 in Ubuntu 14.04 LTS 64 bit. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE

need your help for the following vhdl code in the Xilinx tool

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity conv_enc is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; inp : in STD_LOGIC; outp : out STD_LOGIC_VECTOR(3 DOWN TO 0)); end conv_enc; a

In Verilog, the vector array part selection reg is illegal

reg [data_width-1:0]coeff[0:order-1]; wire[3:0]lsbcoeff; wire [7:4]msbcoeff; lsbcoeff = coeff[3:0]; msbcoeff = coeff[7:4]; In the above line of code, im getting error Part-select of vector reg array 'coeff' is illegal Illegal right hand side of block

Synthetic indexed part selection in verilog

Can I use something like code below (counter value in vector index) in my verilog code? data_out[cnt*32 + 31 : cnt*32] = data_in; Is this construct synthesizable in xst? I've got a constant defined data_out range and cnt is incremented on clock and n

Does the C ++ runtime still require malloc ()?

I have a C++ application running bare-metal that I want to make as small as possible. I am not using dynamic memory allocation anywhere. I am using no STL functions. I've also overridden all the varieties of "delete" and "new" with emp

How to send a fixed number of points to FPGA

I am using Vivado for Zedboard. I have my custom IP contains 32 bit input and output .I need to do some arithmetic operation with fixed point number too. But this fixed point number shall be sent from SDK to FPGA part. So my question is how to repres

How can I design VHDL modal in the following details?

Design VHDL model of a functional unit called sign-extender unit used in some processors. Input of this unit is 4-bit signed binary number and output is 8 bit signed binary number. The unit preserves magnitude and sign of the number. Here is my code

The SPI interface works in simulation but not on real hardware

I am trying to send multiple bytes on the SPI bus during the transmit window. Initially I am acquiring data from the flash ADC when the input pulse is high, then calculating its average and transmitting each average value sequentially on the SPI bus.

Why does this code to increment a uint8_t include "& 0xFF"?

When reading through some example codes for DMAs from Xilinx, I came across this piece of code: value = (value + 1) & 0xFF where value is an uint8_t. What is the point of the & 0xFF? Why not simply write value = value + 1?My guess is that this cod

You can not run ET bank testbench?

This is my code: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY AND_Bank_Test IS END AND_Bank_Test; ARCHITECTURE behavior OF AND_Bank_Test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT AND_Bank PORT( Input : IN std_logic_vect

Latch duplication in the scheme of technology (vhdl)

Please note, this is a study question. I have to describe a simple d-latch in vhdl, and then synthesize it. The problem is that it is a "unary" d-latch, and its single input is mapped directly to its outputs (Q and nQ). You can imagine it as a c

Cross-compilation program that uses pthreads for bare metal

OK, this might be a very general question but I'm not to familiar with the topic and happy for any hint. I have a Cross Compiling tool chain from SoucereyCodeBench for ARM ( arm-xilinx-linux-gnueabi-). I cross compiled a library which uses the compil

Why does my VHDL code have locks?

* I'm coding VHDL in Xilinx 14.3 and am targeting the Nexys 2 board.* From what I've read, latches come from there being incomplete if/case statements or when an output isn't set in all possible paths. I've looked over my code multiple times and am s

Make a simple circuit to dissipate power in VHDL

I'm looking for ideas on something simple to write that I can use to measure power. I just need it to make sure that my power measurement is working. I'm using Xilinx ISE 14.1 on a Virtex-6. I'd like a simple circuit to write and to synthesize. So fa

VHDL: can not have such operands in this context (sobel filter)

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; --use ieee.std_logic_signed.all; entity sobel is port ( top_left_pixel : in std_logic; top_middle_pixel : in std_log

Weird XNOR behavior in VHDL

The code that is causing problems looks like a normal xnor operation as you can see below: S(1) <= L(16) xnor L(26); This line causes the following error: ncvhdl_p: *E,EXPSMI (HDL/aes_sbox_enc_depth16.vhd,169|14): expecting a semicolon (';') [9.5.1].

Define a method to register in vhdl

Is is possible to define something like OOP-style instance method for a record in VHDL to be recognized by XST? For a record type rectangle: type rectangle is record x : integer; y : integer; width : integer; height : integer; end record; I'd like to

Generate a state machine graph from a VHDL code?

Is there any quite good tool to generate State Machine graph from VHDL code? I'm using Xilinx ISE Webpack. Cheers!Active HDL has a feature called "Code2Graphics" which supports this. Additionally, some synthesis tools (typically ones you would h

Understanding the sync signal in Xilinx Simulink

I am having some trouble understanding the concept of Timing Signals in Simulink (Xilink Library). I will explain with an example, Suppose you have a serial Bitstream and you would like to take the sum of Odd and Even Bit, So you would probably write

Why is the standard IEEE vhdl library not STL?

IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV components/operator. It seems that Altera's MAX+P

Xilinx Microblaze C and assembly

I have an application written in C for a Xilinx Microblaze core. However, the performance isn't quite what I want so I was considering rewriting some of the core functions in assembly. I'm having trouble figuring out how to get Xilinx Platform Studio