The VHDL package does not compile

I am new to VHDL and I'm using VIvado 2017.1. I'm trying to use a package to define constants and other such enumerated types to include in multiple models. Right now however, I am unable to use the package in my model. I keep getting Error: Cannot f

Xilinx device-specific primitives

I need a list of device-specific primitives of Xilinx devices. I know that ISE has a list of templates and there are also PDF user guides but I need them as list of files in a folder so that I can parse them and extract name and port-list of every mo

How to add a Linux kernel driver module as a Buildroot package?

I am currently building an Embedded Linux for my Zybo Board from Xilinx. For this I use Buildroot. Now I want to add a driver, written in C, which can be used by a user program to write to some specific registers, enabling it to control some LEDs. Wh

Use a type before it is declared in VHDL (2008)

Is it possible in any version of VHDL, maybe in 2008, to use a type before it's declared? E.g. I have this array declaration in the architecture of an entity: type my_array is array (integer range <>) of my_type; And still in the same architecture s

need your help for the following vhdl code in the Xilinx tool

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity conv_enc is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; inp : in STD_LOGIC; outp : out STD_LOGIC_VECTOR(3 DOWN TO 0)); end conv_enc; a

SDN laboratory with NETFPGA-1g card and projector

I'am creating an SDN lab with NETFPGA-1g card and floodlight as controller, but I can't get floodlight controller to connect with the card (Not in localhost). I gave a static ip address to the controller and typed it the netfpga. The controller kept

In Verilog, the vector array part selection reg is illegal

reg [data_width-1:0]coeff[0:order-1]; wire[3:0]lsbcoeff; wire [7:4]msbcoeff; lsbcoeff = coeff[3:0]; msbcoeff = coeff[7:4]; In the above line of code, im getting error Part-select of vector reg array 'coeff' is illegal Illegal right hand side of block

Synthetic indexed part selection in verilog

Can I use something like code below (counter value in vector index) in my verilog code? data_out[cnt*32 + 31 : cnt*32] = data_in; Is this construct synthesizable in xst? I've got a constant defined data_out range and cnt is incremented on clock and n

the implementation of a 50ns delay in VHDL

I'm sending data to and A/D converter and I need the command data to be delayed at least 50ns from clk_19khz. Here is what I have so far. How do I insert a delay of 50ns which is a requirement for the A/D between the clk_19khz and my first Dout bit t

Does the C ++ runtime still require malloc ()?

I have a C++ application running bare-metal that I want to make as small as possible. I am not using dynamic memory allocation anywhere. I am using no STL functions. I've also overridden all the varieties of "delete" and "new" with emp

How to send a fixed number of points to FPGA

I am using Vivado for Zedboard. I have my custom IP contains 32 bit input and output .I need to do some arithmetic operation with fixed point number too. But this fixed point number shall be sent from SDK to FPGA part. So my question is how to repres

Verilog Advanced Design Analysis

I'm trying to implement a design into a Virtex II Pro FPGA (from Xilinx). The problem is the design is overmapped, taking up too many resources. To overcome that, I needed to know which blocks of my code are the most demanding (require more resources

How can I design VHDL modal in the following details?

Design VHDL model of a functional unit called sign-extender unit used in some processors. Input of this unit is 4-bit signed binary number and output is 8 bit signed binary number. The unit preserves magnitude and sign of the number. Here is my code

Led signal can not be synthesized, bad synchronous description?

I have created a frequency divider, and I want to test it using a FPGA board. To test it I want to make a led flicker with the divided frequency, if a switch is on. The problem is that I do't know how to change the value of the led if clock is not on

You can not run ET bank testbench?

This is my code: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY AND_Bank_Test IS END AND_Bank_Test; ARCHITECTURE behavior OF AND_Bank_Test IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT AND_Bank PORT( Input : IN std_logic_vect

Latch duplication in the scheme of technology (vhdl)

Please note, this is a study question. I have to describe a simple d-latch in vhdl, and then synthesize it. The problem is that it is a "unary" d-latch, and its single input is mapped directly to its outputs (Q and nQ). You can imagine it as a c

Conditional UCF statements or inclusion of conditional UCF file

Is there a way/workaround to use statements in a UCF file conditionally, or, can UCF files be included into other UCF files conditionally? The problem I'm facing is that I have a top module with a set of generics which conditionally instantiate or re

The signal is connected to several following drivers

I trying to run the following and I receive this error: Here's the Verilog code: module needle( input referrence,input penalty,output index[7:0]); //inout input_itemsets; //input referrence; //input penalty; //output index; parameter max_cols=8; // w

Cross-compilation program that uses pthreads for bare metal

OK, this might be a very general question but I'm not to familiar with the topic and happy for any hint. I have a Cross Compiling tool chain from SoucereyCodeBench for ARM ( arm-xilinx-linux-gnueabi-). I cross compiled a library which uses the compil

Moving data between processes in Spartan 3

I have two processes A and B, each with its own clock input. The clock frequencies are a little different, and therefore not synchronized. Process A samples data from an IC, this data needs to be passed to process B, which then needs to write this da

New in VHDL, the unaffected waveform is not supported

I'm using VHDL, but my simulator doesnt support the unaffected waveform in the following example code which I need to have running before I can begin the homework assignment. I read online I can pass the same waveform Z, but I'm not sure how to do th

if the behavior elsif vhdl

I am using webPack ISE v 13 to program a Nexys 3 board with the following piece of code and notice completely different behavior by swapping statements in the if elsif statement. In essence, I'm using three pushbuttons on the board: when pressing the

VHDL: can not have such operands in this context (sobel filter)

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; --use ieee.std_logic_signed.all; entity sobel is port ( top_left_pixel : in std_logic; top_middle_pixel : in std_log

Weird XNOR behavior in VHDL

The code that is causing problems looks like a normal xnor operation as you can see below: S(1) <= L(16) xnor L(26); This line causes the following error: ncvhdl_p: *E,EXPSMI (HDL/aes_sbox_enc_depth16.vhd,169|14): expecting a semicolon (';') [9.5.1].

Define a method to register in vhdl

Is is possible to define something like OOP-style instance method for a record in VHDL to be recognized by XST? For a record type rectangle: type rectangle is record x : integer; y : integer; width : integer; height : integer; end record; I'd like to

Generate a state machine graph from a VHDL code?

Is there any quite good tool to generate State Machine graph from VHDL code? I'm using Xilinx ISE Webpack. Cheers!Active HDL has a feature called "Code2Graphics" which supports this. Additionally, some synthesis tools (typically ones you would h

Understanding the sync signal in Xilinx Simulink

I am having some trouble understanding the concept of Timing Signals in Simulink (Xilink Library). I will explain with an example, Suppose you have a serial Bitstream and you would like to take the sum of Odd and Even Bit, So you would probably write