some questions about the method of use DEFINE in NCVERILOG

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I have try use define to simplify the writing and all the parameters are really written

//...
parameter  BLEZ = 1001011;
parameter  BLTZ = 1001100;
parameter  SRA  = 1001101;

`define R_type1 ((op == MOVA)||(op == MOVB)||(op == ADD)||(op == SUB)||(op == AND)||(op == OR)||(op == XOR)||(op == NOT)||(op == SLT))
`define R_type2 ((op == LSL)||(op == LSR)||(op == SRA))
`define JR_type ((op == JMR))
`define J_type  ((op == JMP))
`define I_type  ((op == ADI)||(op == SBI)||(op == ANI)||(op == ORI)||(op == XRI)||(op == AIU)||(op == SIU)(op == JML))
`define LW  ((op == LD))
`define SW  ((op == ST))
`define Branch  ((op == BZ)||(op == BNZ)||(op == BGEZ)||(op == BGTZ)||(op == BLEZ)||(op == BLTZ))

[email protected](op)
begin
RegWrite_id    = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
RegDst_id      = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
MemWrite_id    = 1;//(`SW);
MemRead_id     = (`LW);
MemToReg_id    = (`LW);
ALUSrcA_id     = (`R_type2);
ALUSrcB_id     = (`I_type);
PCSource       = {`JR_type,`J_type,Z};
end

I think there are nothing wrong in logic level but it always gave some ERROR like this:

RegWrite_id    = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                        |
ncvlog: *E,EXPRPA (Decode_Unit.v,71|56): expecting a right parenthesis (')') [4.3][9.7(IEEE)].
(`define macro: I_type [Decode_Unit.v line 64], file: Decode_Unit.v line 71)
RegWrite_id    = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                          |
ncvlog: *E,EXPSMC (Decode_Unit.v,71|58): expecting a semicolon (';') [9.2.2(IEEE)].
RegWrite_id    = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                          |
ncvlog: *E,NOTSTT (Decode_Unit.v,71|58): expecting a statement [9(IEEE)].
RegDst_id      = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
               |
ncvlog: *E,EXPLPA (Decode_Unit.v,72|15): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
RegDst_id      = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                        |
ncvlog: *E,EXPRPA (Decode_Unit.v,72|56): expecting a right parenthesis (')') [4.3][9.7(IEEE)].
(`define macro: I_type [Decode_Unit.v line 64], file: Decode_Unit.v line 72)
RegDst_id      = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                          |
ncvlog: *E,EXPSMC (Decode_Unit.v,72|58): expecting a semicolon (';') [12.1.2][7.1(IEEE)].
MemWrite_id    = 1;//(`SW);
               |
ncvlog: *E,EXPLPA (Decode_Unit.v,73|15): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
MemRead_id     = (`LW);

and all the parameters are really written

it's confusing....
please give me some coaching


You forgot an || operator between the last two terms in the I_type macro.

Also note that if you want your parameters to be interpreted as binary number, you will have to add 'b in front of them, example 'b1010 is the number ten in binary while 1010 is one thousand and ten.